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Proceedings Paper

Lifting folded pipelined discrete wavelet packet transform architecture
Author(s): Guillermo Paya; Marcos M. Peiro; J. Francisco Ballester; Vicente Herrero; Francisco Mora
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Paper Abstract

The present article describes a new high-efficient architecture for 1-D discrete wavelet packet transform (DWPT) base on lifting, folded and pipeline techniques, which makes possible to expand three completes levels. An architecture for a CDF(2,2) wavelet base is proposed. We have designed a filter bank using a lifting factorization for these coefficients and we have used an extension of the recursive pyramid algorithm (RPA) to obtain the three complete levels. We have pipelined our architecture to reach a maximally fast structure with only one logic operator in the critical path. Moreover, our architecture performances 75 % of hardware utilization for a DWPT realization. A comparative is presented between our DWPT architecture with others DWPT architectures. Our proposal lifting pipelined DWPT architecture is a maximally fast structure with only one logic operator in the critical path. Others DWPT architectures are based on memory access, that implies lower operation frequency and higher power consumption as our architecture.

Paper Details

Date Published: 21 April 2003
PDF: 8 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.498992
Show Author Affiliations
Guillermo Paya, Univ. Politecnica de Valencia (Spain)
Marcos M. Peiro, Univ. Politecnica de Valencia (Spain)
J. Francisco Ballester, Univ. Politecnica de Valencia (Spain)
Vicente Herrero, Univ. Politecnica de Valencia (Spain)
Francisco Mora, Univ. Politecnica de Valencia (Spain)

Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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