Share Email Print

Proceedings Paper

Scaling down photonic waveguide devices on the SOI platform
Author(s): Pavel Cheben; Dan-Xia Xu; Siegfried Janz; Andre Delage
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

We discuss the challenges encountered when scaling down photonic waveguide devices, and demonstrate possible solutions in silicon-on-insulator (SOI) platform. First, sources of waveguide birefringence such as waveguide geometry and stress in the waveguiding layer are discussed. Birefringence sensitivity to inaccuracy of waveguide dimensions is compared for different waveguide geometries, including trapezoidal and rectangular cross-sections. Results show that trapezoidal waveguides are more robust, which makes fabrication tolerances less stringent. Methods for minimizing the waveguide birefringence using stress induced by an over-cladding dielectric film, and by inducing form birefringence through deposition of thin layers of high and low refractive index materials, are discussed. Compact arrayed waveguide grating (AWG) devices are presented, with internal loss of -5.9 dB, crosstalk better than -20 dB, and polarization dependent wavelength shift of <0.05 nm. We discuss and quantify the sources of loss and crosstalk in our AWG devices, and review the methods we have developed for compensation of the polarization dependent wavelength shift, including etched compensator and silicon-oxide-silicon (SOS) compensator. The latter exploits form birefringence of a thin buried oxide layer sandwiched between silicon waveguide core and a silicon over-layer, and is simple to fabricate by standard oxide and amorphous silicon or polysilicon deposition techniques. The calculated loss penalty of the SOS compensator is less than 0.2 dB for both TE and TM polarization.

Paper Details

Date Published: 21 April 2003
PDF: 10 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.498795
Show Author Affiliations
Pavel Cheben, National Research Council Canada (Canada)
Dan-Xia Xu, National Research Council Canada (Canada)
Siegfried Janz, National Research Council Canada (Canada)
Andre Delage, National Research Council Canada (Canada)

Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

© SPIE. Terms of Use
Back to Top