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Proceedings Paper

Simulation of void formation in interconnect lines
Author(s): Alireza Sheikholeslami; Clemens Heitzinger; Helmut Puchner; Fuad Badrieh; Siegfried Selberherr
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Paper Abstract

The predictive simulation of the formation of voids in interconnect lines is important for improving capacitance and timing in current memory cells. The cells considered are used in wireless applications such as cell phones, pagers, radios, handheld games, and GPS systems. In backend processes for memory cells, ILD (interlayer dielectric) materials and processes result in void formation during gap fill. This approach lowers the overall k-value of a given metal layer and is economically advantageous. The effect of the voids on the overall capacitive load is tremendous. In order to simulate the shape and positions of the voids and thus the overall capacitance, the topography simulator ELSA (Enhanced Level Set Applications) has been developed which consists of three modules, a level set module, a radiosity module, and a surface reaction module. The deposition process considered is deposition of silicon nitride. Test structures of interconnect lines of memory cells were fabricated and several SEM images thereof were used to validate the corresponding simulations.

Paper Details

Date Published: 21 April 2003
PDF: 8 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.498783
Show Author Affiliations
Alireza Sheikholeslami, Technische Univ. Wien (Austria)
Clemens Heitzinger, Technische Univ. Wien (Austria)
Helmut Puchner, Cypress Semiconductor Corp. (United States)
Fuad Badrieh, Cypress Semiconductor Corp. (United States)
Siegfried Selberherr, Technische Univ. Wien (Austria)


Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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