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Proceedings Paper

System-level verification methodology for advanced switch fabrics
Author(s): Javier Sosa; Juan A. Montiel-Nelson; Hector Navarro; Mahendra V. Shahdadpuri; Roberto Sarmiento
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Paper Abstract

A system-level verification methodology for advanced switch fabrics is introduced in this paper. Verification is getting more time-consuming as design complexity increases and typically consumes over half of the design effort. Writing testbenches in an ad-hoc verification environment, such as Verilog, VHDL or in C/C++ using PLI directly, is tedious, unproductive and the reusability is low. Time-to-market is critical at chip-level verification, if we add the short life cycles and the changing standards, the design and verification of new products require new design and verification tools. As result of our methodology a verification framework is also presented. The decomposition of each interface of the switch fabric allows the reconfiguration of the framework, when there is a new revision of one design. This idea promotes the reuse of the main interface code and verification statements. The development of the verification framework in C++, 'e' and Verilog demonstrates that our methodology can be applied independently of the programming language. New features, added to the framework such as error insertion, give a highest control over the verification and they enhance the verification coverage in corner case mode. On the other hand, the golden reference layer is the key of the automatic mode, because a high level model can be used as reference to check the correctness of the DUV automatically and the synchronization issues are resolved between the different simulator natures. Several commercial and non-commercial advanced switch fabrics have been verified using this method. The highest complexity verified circuits were VSC882/VSC872 (GigaStream Chip Set). The usefulness of the proposed methodology is demonstrated by GigaStream Chip Set functional success and the saving of a 60% in the verification time per effort unit. In general, given a programming language, the improvement of using our methodology is around a 40% in verification time per effort unit.

Paper Details

Date Published: 21 April 2003
PDF: 12 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.498612
Show Author Affiliations
Javier Sosa, Univ. de Las Palmas de Gran Canaria (United States)
Juan A. Montiel-Nelson, Univ. de Las Palmas de Gran Canaria (Spain)
Hector Navarro, Univ. de Las Palmas de Gran Canaria (Spain)
Mahendra V. Shahdadpuri, Univ. de Las Palmas de Gran Canaria (Spain)
Roberto Sarmiento, Univ. de Las Palmas de Gran Canaria (Spain)


Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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