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Proceedings Paper

Systolic array architecture of a new VLSI vision chip
Author(s): Robert W. Means
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Paper Abstract

A new type of high performance VLSI systolic array is presented that is able to perform two- dimensional convolution with kernels sizes large than the physical array of processing elements. This array is particularly well-suited for neural network image processing algorithms that use large connected neighborhoods to model the transformations between layers of neurons. The new VLSI systolic array can also perform the two-dimensional convolution with the small kernels (such as 3 X 3) that are often used in the more standard image processing. In addition, the systolic array can perform one-dimensional convolution and matrix-vector multiplication. The interface of the array to external memory is designed such that a conventional linear memory architecture is used for accessing and storing data. No variable length scan conversion shift registers are needed by the systolic array to access an image stored in a conventional raster scan format. Such scan conversion variable length shift registers are often required with other systolic array architectures. The VLSI array is extendible so that both a single chip and a multiple chip architecture system can be built.

Paper Details

Date Published: 1 December 1991
PDF: 6 pages
Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); doi: 10.1117/12.49849
Show Author Affiliations
Robert W. Means, HNC, Inc. (United States)

Published in SPIE Proceedings Vol. 1566:
Advanced Signal Processing Algorithms, Architectures, and Implementations II
Franklin T. Luk, Editor(s)

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