Share Email Print
cover

Proceedings Paper

Transfer of single-crystalline silicon nanolayer onto an alien substrate
Author(s): Alexander Y. Usenko; William N. Carr; Bo Chen
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Starting from 60 nanometer node, next generations of mainstream semiconductor devices (i.e.,CMOS) will be mostly manufactured from silicon-on-insulator (SOI) initial substrates with the top silicon layer having a thickness 50 nm or less. We describe a process that is capable for transfer of nanoscale thick layers. The layer is delaminated from a single crystalline silicon substrate and laminated onto another substrate thus resulting in SOI. The process includes: (1) forming a trap layer for hydrogen in an initial substrate (2) delivery of hydrogen to the traps by diffusion of monatomic hydrogen (3) evolving the trapped hydrogen into a layer of hydrogen platelets (4) stiffening of the surface of the initial substrate by laminating to another substrate (5) delaminating a layer from the initial substrate along the hydrogen platelet layer. Details of the new layer transfer process is described. A depth where the buried trap layer locates is critical for the process. An implantation of heavy ions is used to form the trap layer. A trap capacity for hydrogen is evaluated as a function of implantation conditions. Plasma hydrogenation is used to deliver an atomic hydrogen to the traps. ECR, microwave, rf, and DC plasma are compared as the hydrogenation sources. Dependence of a thickness of a transferred layer as a function of the mass of implanted ions and implantation energy is described. Types of layer transfer faults are described. Mechanisms of the layer transfer faults are suggested. We discuss limits of scaling down of thickness of the layer that is transferred from one substrate to another one. Scaling limit of our process is compared to the limits of other (SIMOX, Smart-cut, and ELTRAN) processes.

Paper Details

Date Published: 29 April 2003
PDF: 8 pages
Proc. SPIE 5118, Nanotechnology, (29 April 2003); doi: 10.1117/12.498456
Show Author Affiliations
Alexander Y. Usenko, Silicon Wafer Technologies Inc. (United States)
William N. Carr, New Jersey Institute of Technology (United States)
Bo Chen, New Jersey Institute of Technology (United States)


Published in SPIE Proceedings Vol. 5118:
Nanotechnology
Robert Vajtai; Xavier Aymerich; Laszlo B. Kish; Angel Rubio, Editor(s)

© SPIE. Terms of Use
Back to Top