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Proceedings Paper

Naval Research Laboratory flex processor for radar signal processing
Author(s): James J. Alter; James B. Evins; J. P. Letellier
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Paper Abstract

This paper describes a programmable radar signal processor architecture developed at the Naval Research Laboratory (NRL). The design incorporates T.I. TMS320C30 programmable digital signal processor devices, Xilinx programmable gate arrays, TRW FFT devices, and a parallel array of Inmos Transputer microprocessors. The architecture is extremely flexible and is applicable to a wide variety of applications.

Paper Details

Date Published: 1 December 1991
PDF: 6 pages
Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); doi: 10.1117/12.49831
Show Author Affiliations
James J. Alter, Naval Research Lab. (United States)
James B. Evins, Naval Research Lab. (United States)
J. P. Letellier, Naval Research Lab. (United States)


Published in SPIE Proceedings Vol. 1566:
Advanced Signal Processing Algorithms, Architectures, and Implementations II
Franklin T. Luk, Editor(s)

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