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Proceedings Paper

CORDIC processor architectures
Author(s): Johann F. Boehme; D. Timmermann; H. Hahn; Bedrich J. Hosticka
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Paper Abstract

As CORDIC algorithms receive more and more attention in elementary function evaluation and signal processing applications, the problem of their VLSI realization has attracted considerable interest. In this work we review the CORDIC fundamentals covering algorithm, architecture, and implementation issues. Various aspects of the CORDIC algorithm are investigated such as efficient scale factor compensation, redundant and non-redundant addition schemes, and convergence domain. Several CORDIC processor architectures and implementation examples are discussed.

Paper Details

Date Published: 1 December 1991
PDF: 12 pages
Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); doi: 10.1117/12.49829
Show Author Affiliations
Johann F. Boehme, Ruhr Univ. Bochum (Germany)
D. Timmermann, Fraunhofer Institute of Microelectronic Circuits and Systems (Germany)
H. Hahn, Fraunhofer Institute of Microelectronic Circuits and Systems (Germany)
Bedrich J. Hosticka, Fraunhofer Institute of Microelectronic Circuits and Systems (Germany)


Published in SPIE Proceedings Vol. 1566:
Advanced Signal Processing Algorithms, Architectures, and Implementations II
Franklin T. Luk, Editor(s)

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