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Proceedings Paper

Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree
Author(s): Naofumi Takagi
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Paper Abstract

An arithmetic unit based on a high-speed multiplier with a redundant binary addition tree is proposed. It is efficient for numerical computations with iteration of multiplications and addition/subtractions. A new multiplier recoding method makes the arithmetic unit efficient for these computations.

Paper Details

Date Published: 1 December 1991
PDF: 8 pages
Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); doi: 10.1117/12.49825
Show Author Affiliations
Naofumi Takagi, Kyoto Univ. (Japan)


Published in SPIE Proceedings Vol. 1566:
Advanced Signal Processing Algorithms, Architectures, and Implementations II
Franklin T. Luk, Editor(s)

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