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Proceedings Paper

Arithmetic processor design for the T9000 transputer
Author(s): Simon C. Knowles
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Paper Abstract

This paper describes aspects of the arithmetic algorithms, architecture, and VLSI engineering of the 64-bit floating-point unit of the T9000 Transputer. The unit is fully conformant to the IEEE-754 floating-point arithmetic standard, and has been implemented in a 1 micrometers , triple- metal CMOS technology. The 160,000 transistor design performs addition in 40 ns, double precision multiplication in 60 ns, and double-precision division or square root in 300 ns. It will sustain 17 MFlops on the Linpac benchmark, yet occupies less than 15 mm2 of silicon--about 8.5% of the die area of T9000.

Paper Details

Date Published: 1 December 1991
PDF: 14 pages
Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); doi: 10.1117/12.49824
Show Author Affiliations
Simon C. Knowles, INMOS Ltd. (United Kingdom)


Published in SPIE Proceedings Vol. 1566:
Advanced Signal Processing Algorithms, Architectures, and Implementations II
Franklin T. Luk, Editor(s)

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