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Proceedings Paper

Leakage control for deep-submicron circuits
Author(s): Kaushik Roy; Hamid Mahmoodi-Meimand; Saibal Mukhopadhyay
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Paper Abstract

High leakage current in deep submicron regime is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are scaled every technology generation. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low power applications. This paper considers various transistor intrinsic leakage mechanisms including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, gate oxide tunneling, and bad-to-band-tunneling and explores different techniques to reduce leakage power consumption for scaled technologies.

Paper Details

Date Published: 21 April 2003
PDF: 12 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.498181
Show Author Affiliations
Kaushik Roy, Purdue Univ. (United States)
Hamid Mahmoodi-Meimand, Purdue Univ. (United States)
Saibal Mukhopadhyay, Purdue Univ. (United States)


Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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