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Proceedings Paper

State of the art in CMOS threshold logic VLSI gate implementations and systems
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Paper Abstract

In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in CMOS. This paper presents a summary of the recent developments in TL circuit design. High-performance TL gate circuit implementations are compared, and a number of their applications in computer arithmetic operations are reviewed. It is shown that the application of TL in computer arithmetic circuit design can yield designs with significantly reduced transistor count and area while at the same time reducing circuit delay and power dissipation when compared to conventional CMOS logic.

Paper Details

Date Published: 21 April 2003
PDF: 12 pages
Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.497792
Show Author Affiliations
Peter Celinski, The Univ. of Adelaide (Australia)
Technische Univ. Delft (Netherlands)
Sorin D. Cotofana, Technische Univ. Delft (Netherlands)
Jose Fco. Lopez, Univ. de Las Palmas de Gran Canaria (Spain)
Said F. Al-Sarawi, The Univ. of Adelaide (Australia)
Derek Abbott, The Univ. of Adelaide (Australia)


Published in SPIE Proceedings Vol. 5117:
VLSI Circuits and Systems
Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis, Editor(s)

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