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Proceedings Paper

Characterization and modeling of intradie variation and its applications to design for manufacturability
Author(s): Sharad Saxena; Carlo Guardiani; Michele Quarantelli; Nicola Dragone; Sean Minehane; Patrick McNamara; Jeff A. Babcock
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Paper Abstract

Device scaling increases the impact of within-die variation or mismatch on the performance and yield of many important components of System on Chip (SoC) designs. This has created a need for accurate characterization, modeling, and simulation of mismatch. This paper provides a brief overview of the recent progress in these areas along with an example illustrating the application of these techniques to Design for Manufacturability (DFM) of Ultra Deep Submicron (UDSM) technologies.

Paper Details

Date Published: 10 July 2003
PDF: 5 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.497477
Show Author Affiliations
Sharad Saxena, PDF Solutions, Inc. (United States)
Carlo Guardiani, PDF Solutions, Inc. (United States)
Michele Quarantelli, PDF Solutions, Inc. (United States)
Nicola Dragone, PDF Solutions, Inc. (United States)
Sean Minehane, PDF Solutions, Inc. (United States)
Patrick McNamara, PDF Solutions, Inc. (United States)
Jeff A. Babcock, PDF Solutions, Inc. (United States)

Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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