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Proceedings Paper

60-nm gate patterning with DUV lithography and resist trimming process
Author(s): Qunying Lin; Michael J. Sack; Kelvin Loh; Yelehanka R. Pradeep; Mousumi Bhat
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Proc. SPIE 4691, Optical Microlithography XV, ; doi: 10.1117/12.490518
Show Author Affiliations
Qunying Lin, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Michael J. Sack, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Kelvin Loh, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Yelehanka R. Pradeep, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Mousumi Bhat, Chartered Semiconductor Manufacturing, Ltd. (Singapore)


Published in SPIE Proceedings Vol. 4691:
Optical Microlithography XV
Anthony Yen, Editor(s)

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