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Proceedings Paper

Low-noise SOI Hall devices
Author(s): Youcef Haddab; Vincent Mosser; Melanie Lysowec; Jan Suski; Laurent Demeus; Christian Renaux; Stéphane Adriensen; Denis Flandre
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Paper Abstract

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring a wide range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

Paper Details

Date Published: 8 May 2003
PDF: 8 pages
Proc. SPIE 5115, Noise and Information in Nanoelectronics, Sensors, and Standards, (8 May 2003); doi: 10.1117/12.490185
Show Author Affiliations
Youcef Haddab, SchlumbergerSema (France)
Vincent Mosser, SchlumbergerSema (France)
Melanie Lysowec, SchlumbergerSema (France)
Jan Suski, SchlumbergerSema (France)
Laurent Demeus, Univ. Catholique de Louvain (Belgium)
Christian Renaux, Univ. Catholique de Louvain (Belgium)
Stéphane Adriensen, Univ. Catholique de Louvain (Belgium)
Denis Flandre, Univ. Catholique de Louvain (Belgium)

Published in SPIE Proceedings Vol. 5115:
Noise and Information in Nanoelectronics, Sensors, and Standards
Laszlo B. Kish; Frederick Green; Giuseppe Iannaccone; John R. Vig, Editor(s)

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