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Proceedings Paper

Comparison of EUV and optical device wafer heating
Author(s): Jaehyuk Chang; Roxann L. Engelstad; Edward G. Lovell
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Paper Abstract

The International Technology Roadmap for Semiconductors requires improvements in resolution for each lithographic node. In essence, all sources of distortion in the chip fabrication process must be minimized to meet the stringent error budgets for the sub-90-nm nodes. These include the thermal distortions of the device wafer caused by energy deposition during exposure. Absorbed energy from the beam produces temperature increases and structural displacements in the wafer, which directly contribute to pattern placement errors and image blur. In this research, the thermomechanical response of the device wafer was investigated and compared for 193-nm lithography and EUV lithography. Thermal and structural finite element (FE) models were developed to numerically simulate the exposure process for both types of tools. The three-dimensional FE models include the full wafer and chuck to identify the time-dependent response. For verification purposes, the FE models were benchmarked against an analytical test case. Since the thermomechanical response is relatively sensitive to exposure energy and wafer chucking, parametric studies were performed to illustrate the effects of resist sensitivity, backside contact conductance, and effective boundary conditions. Results for both 193-nm lithography and EUV lithography are presented.

Paper Details

Date Published: 16 June 2003
PDF: 10 pages
Proc. SPIE 5037, Emerging Lithographic Technologies VII, (16 June 2003); doi: 10.1117/12.490137
Show Author Affiliations
Jaehyuk Chang, Univ. of Wisconsin/Madison (United States)
Roxann L. Engelstad, Univ. of Wisconsin/Madison (United States)
Edward G. Lovell, Univ. of Wisconsin/Madison (United States)


Published in SPIE Proceedings Vol. 5037:
Emerging Lithographic Technologies VII
Roxann L. Engelstad, Editor(s)

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