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Proceedings Paper

Pattern etching and selective growth of GaAs by in-situ electron-beam lithography using an oxidized thin layer
Author(s): K. Akita; Yoshimasa Sugimoto; Mototaka Taneya; Y. Hiratani; Y. Ohki; Hidenori Kawanishi; Yoshifumi Katayama
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Paper Abstract

Pattern etching of GaAs by in situ electron-beam (EB) lithography using an oxidized thin ayer is performed in a multichamber system comprising seven chambers for loading sample exchange sample pre-heating molecular beam epitaxy (MBE) surface treatment etching and surface analysis. The in situ EB lithography process comprises the following steps using the multichamber system: (1 ) preparation of a clean GaAs surface by MBE (2) formation of GaAs oxide as a resist film by photo-oxidation in pure oxygen gas (3) direct patterning of the oxide resist film by EB-induced Cl2 etching (4) 012 gas etching of the GaAs surface as a pattern transfer and (5) removal of residual GaAs oxide layer by heating the wafer above about 600 00 in a vacuum under a partial pressure of arsenic. Overgrowth of GaAs and/or AIGaAs layers is also possible on a patterned GaAs wafer without exposing the surface to air. Damage to the patterned area was evaluated through photoluminescnece measurements and compared with the case of conventional dry etching of GaAs. The results showed that damage was extremely small for EB-induced Cl2 etching. The reason is considered to be due to a difference in momentum transfer from charged particles to the lattice. Selective-area epitaxy using this GaAs oxide layer as a mask film was carried out by combination of EB-induced Cl2 etching and metal organic molecular beam epitaxy (MOMBE) using a separate ultra-high

Paper Details

Date Published: 1 March 1991
PDF: 12 pages
Proc. SPIE 1392, Advanced Techniques for Integrated Circuit Processing, (1 March 1991); doi: 10.1117/12.48963
Show Author Affiliations
K. Akita, Optoelectronics Technology Research Lab. (Japan)
Yoshimasa Sugimoto, Optoelectronics Technology Research Lab. (Japan)
Mototaka Taneya, Optoelectronics Technology Research Lab. (Japan)
Y. Hiratani, Optoelectronics Technology Research Lab. (Japan)
Y. Ohki, Optoelectronics Technology Research Lab. (Japan)
Hidenori Kawanishi, Optoelectronics Technology Research Lab. (Japan)
Yoshifumi Katayama, Optoelectronics Technology Research Lab. (Japan)

Published in SPIE Proceedings Vol. 1392:
Advanced Techniques for Integrated Circuit Processing
James A. Bondur; Terry R. Turner, Editor(s)

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