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Proceedings Paper

Evaluation of alignment marks using ASML ATHENA alignment system in 90-nm BEOL process
Author(s): Chin-Boon Tan; Swee-Hock Yeo; Hui Peng Koh; Chee Kiong Koo; Yee Mei Foong; Yong Kong Siew
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Paper Abstract

As the critical dimension (CD) in integrated circuit (IC) device reduces, the total overlay budget needs to be more stringent. Typically, the allowable overlay error is 1/3 of the CD in the IC device. In this case, robustness of alignment mark is critical, as accurate signal is required by the scanner’s alignment system to precisely align a layer of pattern to the previous layer. Alignment issue is more severe in back-end process partly due to the influenced of Chemical Mechanical Polishing (CMP), which contribute to the asymmetric or total destroy of the alignment marks. In this paper, the performance of different design of alignment marks on 0.10μm echnology wafer has been evaluated using ASML ATHENATM alignment system. For example, segmented marks with smaller dimensions in terms of width and length are used. Narrow marks are preferable due to the space constraint in the scribe lines. The width of NSPM has been shrunk down to 70% of the SPM and the length remains the same. It is a challenge to the alignment system to collect the NSPM signal and provide comparable alignment capability. The evaluations were completed using short loop wafers, which focus on back-end-of-line via and metal layers in a 90nm Cu dual damascene low k process. The results also look into the overlay performance using different alignment strategies. Offline overlay measurements were performed to verify the results.

Paper Details

Date Published: 2 June 2003
PDF: 8 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.487734
Show Author Affiliations
Chin-Boon Tan, Nanyang Technological Univ. (Singapore)
Chartered Semiconductor Mfg., Ltd. (Singapore)
Swee-Hock Yeo, Nanyang Technological Univ. (Singapore)
Hui Peng Koh, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Chee Kiong Koo, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Yee Mei Foong, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Yong Kong Siew, Chartered Semiconductor Manufacturing, Ltd. (Singapore)


Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)

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