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Proceedings Paper

Model-based PPC verification methodology with two dimentional pattern feature extraction
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Paper Abstract

A Novel model-based process proximity correction (PPC) verification methodology is proposed. This methodology features the comparison between actual processed wafers and target CAD data. The new system makes it possible to compare extracted two-dimensional pattern features on actual processed wafers with target pattern features on CAD data at any “hot spot” patterns. The “hot spot” patterns have relatively large CD errors on wafers after PPC in lithography simulation. In addition to this methodology, the model-based PPC verification flow was constructed with a feedback loop of the results. The application of this methodology to the 90nm-node CMOS gate yielded useful information on accurate CD control. The qualitative and quantitative consideration from the results indicated suitable subsequent actions regarding wafer fabrication, mask re-fabrication, PPC re-modeling and PPC re-parameterization in the feedback loop.

Paper Details

Date Published: 26 June 2003
PDF: 10 pages
Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); doi: 10.1117/12.485511
Show Author Affiliations
Kohji Hashimoto, Toshiba Corp. (Japan)
Takeshi Ito, Toshiba Corp. (Japan)
Takahiro Ikeda, Toshiba Corp. (Japan)
Shigeki Nojima, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 5040:
Optical Microlithography XVI
Anthony Yen, Editor(s)

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