Share Email Print
cover

Proceedings Paper

157-nm lithography for 65-nm node SRAM-gate
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

We evaluated the requirements for 65-nm SRAM gate fabrication using attenuated phase shifting masks (att-PSM). Off-axis illumination (OAI) and att-PSM, together with optical proximity correction (OPC) were used as resolution enhancement techniques (RETs) for ultimate resolution. It was shown that the photolithographic parameters of the transmittance of the att-PSM and the illumination conditions for optimum conditions were a transmittance of between 15 and 20% and 3/4 annular illumination. The exposure latitude was simulated to be more than 10.9% at 300-nm defocus for a critical dimension (CD) specification of 10%. It has been demonstrated that a 65-nm SRAM-gate, with a line and space (L/S) ratio limited to 1:2 at the minimum pitch, could be fabricated with sufficient depth of focus (DOF). The pattern transfer was accomplished with a bi-layer process, in which the reactive ion etching (RIE) selectivity between a silicon-containing resist and an organic film is very high. This bi-layer process enabled the application of a very thin resist layer. The conditions described in this paper proved successful for the fabrication of a 65-nm SRAM gate with a good pattern profile despite the resist thickness of less than 120nm.

Paper Details

Date Published: 26 June 2003
PDF: 9 pages
Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); doi: 10.1117/12.485376
Show Author Affiliations
Toshifumi Suganaga, Semiconductor Leading Edge Technologies, Inc. (Japan)
Shigeo Irie, Semiconductor Leading Edge Technologies, Inc. (Japan)
Seiro Miyoshi, Semiconductor Leading Edge Technologies, Inc. (Japan)
Jae-Hwan Kim, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kunio Watanabe, Semiconductor Leading Edge Technologies, Inc. (Japan)
Eiji Kurose, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takamitsu Furukawa, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takuya Hagiwara, Semiconductor Leading Edge Technologies, Inc (Japan)
Toshiyuki Ishimaru, Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshiro Itani, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 5040:
Optical Microlithography XVI
Anthony Yen, Editor(s)

© SPIE. Terms of Use
Back to Top