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Proceedings Paper

Maximization of process window for low-k1 spaces using KrF lithography
Author(s): Shih-Chi Fu; Ching-Sen Kuo; Feng-Jia Shiu; Jieh-Jang Chen; Chia-Shiung Tsia; Chia-Tong Ho; Chung Wang
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Paper Abstract

The spaces between floating-gate poly-silicon are critical for the electrical properties of advanced non-volatile memory (NVM). However, the patterning of low-k1 semi-dense spaces in NVM cells is more challenging than the patterning of dense lines in DRAM cells as the former is of lower normalized image log slope (NILS) and optical contrast. Many experiments, including various NA/σ trials, binary intensity or attenuated phase-shift masks (AttPSM), application of various sizes of sub-resolution assist feature (SRAF), or even negative-type photoresist (N-PR) by clear-field patterning, are tested and compared for the 140nm spaces with L:S ratio of 3:1 using KrF lithography. Combined with aerial image simulations and a process window analyzer, the optimal process condition was found. The SRAF functions to mimic the environment of dense pattern and thereby extends the process latitude of the semi-dense spaces. But it damages the image pattern if the side-lobe intensity approaches the intensity threshold. The maximum allowable SRAF depends on mask type and field used. Generally speaking, the SRAF should be smaller in bright-field exposure using the negative-type photoresist (N-PR) than in dark-field exposure using the positive-type photoresist (P-PR) application. The N-PR, despite its intrinsic poorer pattern profile and larger line-edge-roughness as contributed from photoresist effect, was found to surpass the P-PR in process window. A trade-off among process window, mask error enhancement factor (MEEF), pattern profile and mask cost is unavoidable to the selection of mask type or mask bias, and is considered in this paper in the last.

Paper Details

Date Published: 26 June 2003
PDF: 12 pages
Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); doi: 10.1117/12.485360
Show Author Affiliations
Shih-Chi Fu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Ching-Sen Kuo, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Feng-Jia Shiu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Jieh-Jang Chen, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Chia-Shiung Tsia, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Chia-Tong Ho, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Chung Wang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)

Published in SPIE Proceedings Vol. 5040:
Optical Microlithography XVI
Anthony Yen, Editor(s)

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