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Proceedings Paper

Limits of strong phase-shift patterning for device research
Author(s): Michael Fritze; Renee D. Mallen; Bruce Wheeler; Donna Yost; John P. Snyder; Bryan S. Kasprowicz; Benjamin George Eynon; Hua-Yu Liu
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Paper Abstract

Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.

Paper Details

Date Published: 26 June 2003
PDF: 17 pages
Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); doi: 10.1117/12.485332
Show Author Affiliations
Michael Fritze, MIT Lincoln Lab. (United States)
Renee D. Mallen, MIT Lincoln Lab. (United States)
Bruce Wheeler, MIT Lincoln Lab. (United States)
Donna Yost, MIT Lincoln Lab. (United States)
John P. Snyder, Spinnaker Semiconductor (United States)
Bryan S. Kasprowicz, Photronics Inc. (United States)
Benjamin George Eynon, Photronics Inc. (United States)
Hua-Yu Liu, Numerical Technologies, Inc. (United States)


Published in SPIE Proceedings Vol. 5040:
Optical Microlithography XVI
Anthony Yen, Editor(s)

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