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Proceedings Paper

Microeconomics of yield learning in semiconductor manufacturing
Author(s): Kevin M. Monahan
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Paper Abstract

Simple microeconomic models that directly link yield learning to profitability in semiconductor manufacturing have been rare or non-existent. In this work, we review such a model and provide links to inspection capability and cost. Using a small number of input parameters, we explain current yield management practices in 200mm factories. The model is then used to extrapolate requirements for 300mm factories, including the impact of technology transitions to 130nm design rules and below. We show that the dramatic increase in value per wafer at the 300mm transition becomes a driver for increasing metrology and inspection capability and sampling. These analyses correlate well wtih actual factory data and often identify millions of dollars in potential cost savings. We demonstrate this using the example of grating-based overlay metrology for the 65nm node.

Paper Details

Date Published: 2 July 2003
PDF: 16 pages
Proc. SPIE 5043, Cost and Performance in Integrated Circuit Creation, (2 July 2003); doi: 10.1117/12.485288
Show Author Affiliations
Kevin M. Monahan, KLA-Tencor Corp. (United States)


Published in SPIE Proceedings Vol. 5043:
Cost and Performance in Integrated Circuit Creation
Alfred K. K. Wong; Kevin M. Monahan, Editor(s)

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