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Proceedings Paper

Cost-effective strategies for ASIC masks
Author(s): Dipankar Pramanik; Henry H. Kamberian; Christopher J. Progler; Michael Sanie; David Pinto
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Paper Abstract

It is suggested that the high cost of mask sets for 90nm and below technologies may restrict the application of technologies to a handful of high volume chips. Most of the cost for mask production is a result of the increased time to write and inspect (including defect disposition) a mask due to the large files that are created prior to mask writing. Stringent mask specifications needed for low k factor imaging drive protracted and costly yield learning curves for a mask maker. The cost of different steps in the flow from design tape-out to final wafer test are analyzed and it is shown that limiting the reticle field size on critical layers could reduce net costs. The net die cost is lower as long as the number of processed wafers stays below a cutoff number. Costs can be further decreased by reducing the overall "figure count" (and hence writing time) for an ASIC chip by restricting the amount of OPC done on critical layers.

Paper Details

Date Published: 2 July 2003
PDF: 11 pages
Proc. SPIE 5043, Cost and Performance in Integrated Circuit Creation, (2 July 2003); doi: 10.1117/12.485280
Show Author Affiliations
Dipankar Pramanik, Numerical Technologies Inc. (United States)
Henry H. Kamberian, Photronics Inc. (United States)
Christopher J. Progler, Photronics Inc. (United States)
Michael Sanie, Numerical Technologies Inc. (United States)
David Pinto, Numerical Technologies Inc. (United States)


Published in SPIE Proceedings Vol. 5043:
Cost and Performance in Integrated Circuit Creation
Alfred K. K. Wong; Kevin M. Monahan, Editor(s)

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