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Proceedings Paper

Electrical validation of resolution enhancement techniques
Author(s): Kunal N. Taravade; Neal P. Callan; Ebo H. Croffie; Aftab Ahmad
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Paper Abstract

A number of techniques are used for resolution enhancement in leading edge lithography. As feature dimensions shrink, these resolution enhancement techniques (RETs) become more aggressive, causing huge increases in data volume, complexity and write time. The results of these techniques are verified using methods such as SEM measurements of resist or etched structures on the wafer. These RETs tend to either over or under-compensate by way of the suggested corrections or enhancements with respect to the actual device operation. In addition, the systematic and random metrology errors inherent in wafer level top-down SEM measurements become more significant as feature sizes shrink and tolerances become tighter. These errors further cloud the decision as to which RET is most suitable and necessary. To overcome these problems, we have designed an electrical test vehicle which targets those geometries most prevalent in the cells for a given technology. Electrical test (E-test) structures are then varied around these geometries covering the design rule space. Device parameters are measured over this design space for various RETs. This method reconciles the accuracy or effectiveness of RET models using electrical device parameters and uses the same to choose the RET which results in the lowest NRE while at the same time meeting all electrical requirements.

Paper Details

Date Published: 2 July 2003
PDF: 9 pages
Proc. SPIE 5043, Cost and Performance in Integrated Circuit Creation, (2 July 2003); doi: 10.1117/12.485275
Show Author Affiliations
Kunal N. Taravade, LSI Logic Corp. (United States)
Neal P. Callan, LSI Logic Corp. (United States)
Ebo H. Croffie, LSI Logic Corp. (United States)
Aftab Ahmad, LSI Logic Corp. (United States)


Published in SPIE Proceedings Vol. 5043:
Cost and Performance in Integrated Circuit Creation
Alfred K. K. Wong; Kevin M. Monahan, Editor(s)

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