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Proceedings Paper

Design-to-process integration: optimizing 130-nm X architecture manufacturing
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Paper Abstract

The X Architecture is a novel on-chip interconnect architecture based on the pervasive use of diagonal wiring. This diagonal wiring reduces total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, a cost. Thirty percent or greater reduction in via counts is a compelling feature for IC design - but can chips with massive amounts of diagonal wiring be manufactured without some other penalty? This paper presents the result of a project, collaborated by Cadence Design Systems, Numerical Technologies, DuPont Photomasks, and Nikon, aimed at optimizing each step of the lithography supply chain for the Architecture from masks to wafers at 130 nm.

Paper Details

Date Published: 10 July 2003
PDF: 8 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.485258
Show Author Affiliations
Robert Dean, Cadence Design Systems, Inc. (United States)
Vinod K. Malhotra, Numerical Technologies, Inc. (United States)
Nahid King, Numerical Technologies, Inc. (United States)
Michael Sanie, Numerical Technologies, Inc. (United States)
Susan S. MacDonald, DuPont Photomasks, Inc. (United States)
James D. Jordan, DuPont Photomasks, Inc. (United States)
Shigeru Hirukawa, Nikon Corp. (Japan)

Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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