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Proceedings Paper

Creation and verification of phase-compliance SoC IP for the fabless COT designers
Author(s): Vinod K. Malhotra; Nahid King; Raymond Leung; Zain Zia; Shakeel Jeeawoody
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Paper Abstract

As the semiconductor industry has began production of subwavelength geometries, technologies such as Optical Proximity Correction (OPC) and Phase-Shifting Masks (PSM) have become requirements in producing integrated circuits. One of these approaches, Alternating PSM (AltPSM), has been adopted by leading edge semiconductor companies to meet IC manufacturing production requirements. As part of a complete production flow for these processes, it is required for SOC IP to be "phase compliant". Only through the phase compliance, the fabless COT semiconductor market is enabled to leverage the benefits of subwavelength geometries. This paper introduces the concept of phase compliance, and the importance of guaranteeing correct phase topology and phase compliance of layouts for AltPSM. It further proposes a method to create phase compliant SoC IP, and a process of verifying that SoC IP is phase compliance. The timing characterizaitn data is also included to show that the performance speed of the memory layouts was enhanced by 20% over regular 0.13 micron proces. The paper concludes with some general remarks on how this methodolgy will be impacted as we move to 65nm node.

Paper Details

Date Published: 10 July 2003
PDF: 8 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.485257
Show Author Affiliations
Vinod K. Malhotra, Numerical Technologies, Inc. (United States)
Nahid King, Numerical Technologies, Inc. (United States)
Raymond Leung, Virage Logic Corp. (United States)
Zain Zia, Virage Logic Corp. (United States)
Shakeel Jeeawoody, Virage Logic Corp. (United States)


Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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