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Proceedings Paper

Layout optimization at the pinnacle of optical lithography
Author(s): Lars W. Liebmann; Greg A. Northrop; James Culp; Leon Sigal; Arnold Barish; Carlos A. Fonseca
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Paper Abstract

This paper attempts to shed more light on the widely acknowledged need to improve the manufacturabilty of itnegrated chip layouts for sub-100nm technology nodes. After reviewing the parametric performance targets and tiem constaints of the 65nm and 45nm technology nodes, the paper elaborates on the principles of popular resolution enhancement techniques, their impact on chip layouts, and the opportunity for borad layout improvement which they afford. Finally, the viability and feasibility of layout optimization based on a design-for-manufacturability mantra and enabled through "radically design restrictions" is explored.

Paper Details

Date Published: 10 July 2003
PDF: 14 pages
Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.485245
Show Author Affiliations
Lars W. Liebmann, IBM Microelectronics Div. (United States)
Greg A. Northrop, IBM Corp. (United States)
James Culp, IBM Microelectronics Div. (United States)
Leon Sigal, IBM Corp. (United States)
Arnold Barish, IBM Corp. (United States)
Carlos A. Fonseca, IBM Microelectronics Div. (United States)

Published in SPIE Proceedings Vol. 5042:
Design and Process Integration for Microelectronic Manufacturing
Alexander Starikov, Editor(s)

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