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Proceedings Paper

Effects of processing parameters on line-width roughtness
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Paper Abstract

Line width roughness (LWR), transferred from a patterned photoresist to a gate during the etch process, may have a significant effect on the device performance beginning with the 65 nm technology node. Two factors that make LWR a greater concern for this node than for previous technology nodes are: 1) LWR does not scale in proportion to the critical dimensions (CDs), and 2) LWR has been shown to increase as film thickness decreases. A significant challenge for this technology node is the development of a resist process with sufficiently low LWR. In this paper, we investigate the effect that changing processing conditions has on LWR. We begin by reviewing the literature to determine which processing parameters have been shown to impact LWR. We then present experimental results that show how variations in processing parameters affect LWR. We conclude with molecular data showing the relation between resist surface roughness and LWR.

Paper Details

Date Published: 12 June 2003
PDF: 9 pages
Proc. SPIE 5039, Advances in Resist Technology and Processing XX, (12 June 2003); doi: 10.1117/12.485162
Show Author Affiliations
Bryan J. Rice, Intel Corp. (United States)
Heidi B. Cao, Intel Corp. (United States)
Manish Chandhok, Intel Corp. (United States)
Robert P. Meagley, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 5039:
Advances in Resist Technology and Processing XX
Theodore H. Fedynyshyn, Editor(s)

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