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Proceedings Paper

Fabrication of integrated circuits with high yield using ultrathin resist processes
Author(s): Richard D. Peters; Sergei V. Postnikov; Jonathan L. Cobb; S. Dakshina-Murthy; Tab Stephens; Colita Parker; Eric Luckowski; Arturo M. Martinez; Wei Wu; Scott Daniel Hector
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Paper Abstract

We have demonstrated the fabrication of working 130 nm-node SRAMs with high yield using single layer ultra-thin resist (UTR) integrations. Transistor gates were fabricated using 140-nm-thick resist films in combination with a single layer, inorganic anti-reflective coating (ARC) that also acted as a hardmask (HM). An aggressive ARC/HM removal process was developed to enable the use of a thick ARC/HM. The thick ARC/HM was necessary to allow the incorporation of a resist trim step prior to polysilicon gate etch that reduced the transistor gate lengths in silicon from the printed critical dimension (CD) in resist. Transistor performance for both NMOS and PMOS devices with UTR-fabricated gates was equivalent to the performance of standard transistors. Working SRAM arrays were fabricated using UTR at the gate layer that achieved natural yield within 10% of the yield achieved with a thick resist process, and in some cases, with yield that exceeded the thick resist process. CD control for the UTR gate photo process was equivalent to the baseline photo process, and the UTR gate photo process was optimized to increase device yield. Contacts fabricated using 120-nm-thick resist films exhibited electrical characteristics equivalent to those fabricated with standard processes, and yielding SRAM devices were fabricated using UTR at the contact layer. Defect inspection of UTR contact patterning detected the formation of pinholes in the UTR films; however, the formation of pinholes was found to be dependent upon substrate-resist interactions.

Paper Details

Date Published: 12 June 2003
PDF: 12 pages
Proc. SPIE 5039, Advances in Resist Technology and Processing XX, (12 June 2003); doi: 10.1117/12.485122
Show Author Affiliations
Richard D. Peters, Motorola Digital DNA Labs. (United States)
Sergei V. Postnikov, Motorola Digital DNA Labs. (United States)
Jonathan L. Cobb, Motorola Digital DNA Labs. (United States)
S. Dakshina-Murthy, Advanced Micro Devices (United States)
Tab Stephens, Motorola Digital DNA Labs. (United States)
Colita Parker, Motorola Digital DNA Labs. (United States)
Eric Luckowski, Motorola Digital DNA Labs. (United States)
Arturo M. Martinez, Motorola Digital DNA Labs. (United States)
Wei Wu, Motorola Digital DNA Labs. (United States)
Scott Daniel Hector, Motorola Digital DNA Labs. (United States)


Published in SPIE Proceedings Vol. 5039:
Advances in Resist Technology and Processing XX
Theodore H. Fedynyshyn, Editor(s)

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