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Proceedings Paper

Reduction of implantation shadowing effect by dual-wavelength exposure photo process
Author(s): Yiming Gu; Dyiann Chou; Sang Yun Lee; William R. Roche; John L. Sturtevant
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Paper Abstract

As transistor engineering continues to well below 100 nm length devices, ion implantation process tolerances are making these formerly "non-critical" lithography levels more and more difficult. In order to minimize the channeling effect and to obtain a controllable profile of dopant, an angled implantation is often required. However, a shadow area of resist pattern is always accompanied with an angled implantation. This shadowing effect consumes silicon real estate, and reduces the line edge placement (LEP) tolerances. Therefore, methodologies to reduce the shadowing effect in angled implantation become a critical consideration not only for device engineering but also for photolithography. Based on the model analysis, simulation and experiments, this paper presents an effective novel process utilizing dual-wavelength exposure (DWE) to reduce the shadowing effect. The DWE process is realized by two consecutive exposures for an I-line resist with a DUV stepper/scanner and an I-line stepper. The process leverages the high absorption coefficient of novalak-DNQ resist at 248 nm, and results in a tunable post-develop resist thickness to minimize the shadowing effect. It is effective in satisfying the junction requirements and also is helpful in minimizing the number of photoresists in a manufacturing fab. A repeatable resist profile and an excellent CD uniformity across wafer also indicated that the DWE is a potentially manufacturable process.

Paper Details

Date Published: 12 June 2003
PDF: 7 pages
Proc. SPIE 5039, Advances in Resist Technology and Processing XX, (12 June 2003); doi: 10.1117/12.485103
Show Author Affiliations
Yiming Gu, Integrated Device Technology, Inc. (United States)
Dyiann Chou, Integrated Device Technology, Inc. (United States)
Sang Yun Lee, Integrated Device Technology, Inc. (United States)
William R. Roche, Integrated Device Technology, Inc. (United States)
John L. Sturtevant, Integrated Device Technology, Inc. (United States)


Published in SPIE Proceedings Vol. 5039:
Advances in Resist Technology and Processing XX
Theodore H. Fedynyshyn, Editor(s)

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