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Proceedings Paper

Intel's EUV resist development
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Paper Abstract

The success of extreme ultraviolet (EUV) lithography depends upon developing resists that meet the patterning requirements for the technology node in which EUV is inserted. This paper presents Intel’s patterning requirements and development strategies for EUV resists. Two of the primary problems for EUV resists are meeting the linewidth roughness (LWR) requirement, and reducing resist absorbance to obtain good sidewall profiles. Benchmarking data shows that none of the current EUV photoresists meet LWR targets. Modeling results for EUV resists show the impact of resist absorbance on sidewall angle and resolution.

Paper Details

Date Published: 12 June 2003
PDF: 8 pages
Proc. SPIE 5039, Advances in Resist Technology and Processing XX, (12 June 2003); doi: 10.1117/12.485095
Show Author Affiliations
Heidi B. Cao, Intel Corp. (United States)
Jeanette M. Roberts, Intel Corp. (United States)
Janel Dalin, Intel Corp. (United States)
Manish Chandhok, Intel Corp. (United States)
Robert P. Meagley, Intel Corp. (United States)
Eric M. Panning, Intel Corp. (United States)
Melissa K. Shell, Intel Corp. (United States)
Bryan J. Rice, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 5039:
Advances in Resist Technology and Processing XX
Theodore H. Fedynyshyn, Editor(s)

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