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Proceedings Paper

New method for the quantitative evaluation of wafer pattern shape based on CAD data
Author(s): Ryoichi Matsuoka; Masanori Takahashi; Atsushi Uemoto
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Paper Abstract

Semiconductor device manufacturing demands rapid ramp of yield together with feature size reduction, especially for logic and ASIC because of their short-lives and small volume production characteristics. As a technological breakthrough for rapid yield ramp of such devices, we have endeavored to integrate CAD technology with SEM for printed pattern observation, and have developed Grade Scope, an evaluation technology, by combining the wafer proces and upstream design process.

Paper Details

Date Published: 2 June 2003
PDF: 7 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.483688
Show Author Affiliations
Ryoichi Matsuoka, Seiko Instruments Inc. (Japan)
Masanori Takahashi, Seiko Instruments Inc. (Japan)
Atsushi Uemoto, Seiko Instruments Inc. (Japan)

Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)

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