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Proceedings Paper

Ultralow-power operational amplifier CMOS chip for monolithic integration with neural microprobes
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Paper Abstract

A CMOS test chip has been designed and fabricated which can monolithically integrate ultra low-power operational amplifiers with neural microprobes through post-IC processing. Neural microprobes of varying widths (70 μm, 60 μm, 50 μm, and 40 μm) are designed with varying center-to-center spacing (195 μm, 175 μm, 165 μm, 155 μm, 145 μm, and 125 μm) on a test chip for integration. Neural microprobes are first fabricated on a separate Si substrate to develop a fabrication process for post-IC processing for integration. The amplifier is designed in standard 1.5 μm CMOS process for operation at ∓ 0.4 V. Low power performance is realized by combining forward biased source-substrate junction MOSFETs with a novel low-voltage level-shift current mirror. The designed amplifier gives a gain of 7000 (77 dB) and a 3-dB bandwidth of 30 kHz. The amplifier output has a positive offset of only 20 μV and power dissipation of only 40 μW.

Paper Details

Date Published: 22 July 2003
PDF: 7 pages
Proc. SPIE 5055, Smart Structures and Materials 2003: Smart Electronics, MEMS, BioMEMS, and Nanotechnology, (22 July 2003); doi: 10.1117/12.483573
Show Author Affiliations
Chuang Zhang, Louisiana State Univ. (United States)
Tinghui Xin, Louisiana State Univ. (United States)
Ashok Srivastava, Louisiana State Univ. (United States)
Pratul K. Ajmera, Louisiana State Univ. (United States)


Published in SPIE Proceedings Vol. 5055:
Smart Structures and Materials 2003: Smart Electronics, MEMS, BioMEMS, and Nanotechnology
Vijay K. Varadan; Laszlo B. Kish, Editor(s)

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