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Proceedings Paper

Evaluation of alignment target designs for Cu and low-K dual damascene processes
Author(s): Moitreyee Mukherjee-Roy; Navab Singh; Sohan Singh Mehta; Wai Meng Chik; Chin Tiong Sim; Francis Cheong
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Paper Abstract

This paper studies the alignment performance of dual damascene patterning using two different integration schemes. These schemes cater to two different low K materials. The via first scheme is used for CVD type material while the dual hardmask trench first is used for spin on low K material. The alignment and exposure is performed on Nikon scanner S203B using LSA (Laser Step Alignment; a scattering based system) and FIA (Field Interferometer Alignment; a contrast-based system) systems while the overlay is measured on KLA 5200XP. Many different mark designs were evaluated for both the schemes. The effect of resist coat was found to be different on different mark types. Difference was also seen in the signal strengths in X and Y directions. Process optimisation for scanner was done by varying the slice level, signal processing algorithms, and focus. The initial alignment mark evaluations were done by studying the signals obtained from such marks and comparison of Static Random Factor (SRF) and Dynamic Random Factor (DRF) obtained from the scanner. The best marks were then applied to the lot splits and the final performance was evaluated by measuring the total overlay results. Results showed that SRF and DRF evaluation could be used for screening to find out the best marks for a certain level. It can also be concluded that dual damascene alignment is possible with trench first scheme that has small step height using the LSA window mark or the FIA narrow island mark. For both schemes the best performer was the FIA Narrow Island Mark. Hence it can be concluded that better alignment performance could be obtained by special alignment mark designs for a specific level.

Paper Details

Date Published: 2 June 2003
PDF: 10 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.482800
Show Author Affiliations
Moitreyee Mukherjee-Roy, Institute of Microelectronics (Singapore)
Navab Singh, Institute of Microelectronics (Singapore)
Sohan Singh Mehta, Institute of Microelectronics (Singapore)
Wai Meng Chik, Ellipsiz Singapore Pte. Ltd. (Singapore)
Chin Tiong Sim, Ellipsiz Singapore Pte. Ltd. (Singapore)
Francis Cheong, Ellipsiz Singapore Pte. Ltd. (Singapore)

Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)

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