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Proceedings Paper

First review of a suitable metrology framework for the 65-nm technology node
Author(s): Ermes Severgnini; Mauro Vasconi; David Herisson; Philippe Thony
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Paper Abstract

A key enabler to a successful process development and to the device functionality is the introduction of a proper metrology framework, consisting in the selection of the 'correct' tool class for the proposed application on one hand and in the integration of the related measuring procedure into the whole process flow on the other hand. The plan for this work was focused onto the analysis of the main options for critical dimension (CD) measurements targeting to the 65nm technology node, as stated in the International Technology Roadmap for Semiconductors (ITRS) 2001 edition and in the ITRS 2002 update. In order to investigate in deper details the actual status of each selected technique, a list of key characteristics was identified and a comprehensive benchmark performed. Considered techniques include CD-scanning electron microscopy (SEM), CD-scatterometry, CD-atomic force microscopy and 'Combo' approaches. Based upon the data collected during the benchmark phase, suitable procedures to be applied for a proper metrological evaluation of the 65nm node proces development are presented.

Paper Details

Date Published: 2 June 2003
PDF: 12 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.482645
Show Author Affiliations
Ermes Severgnini, STMicroelectronics (Italy)
Mauro Vasconi, STMicroelectronics (Italy)
David Herisson, STMicroelectronics (France)
Philippe Thony, CEA-LETI (France)

Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)

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