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Proceedings Paper

Implementing flare compensation for EUV masks through localized mask CD resizing
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Paper Abstract

Early production EUV exposure tools may have difficulty achieving flare requirements in the 5-6% range for the 32nm technology node. In this case, flare compensation may be needed to achieve the necessary CD control budget for production. This paper explores both experimentally as well as computationally wafer CD compensation though mask CD resizing so that proper CD control across the exposure field can be maintained. Experimental resist data collected on POB#2 of the Engineering Test Stand (ETS) suggest that even a simple linear CD compensation model can signifantly improve CD contorl in the presence of flare variation. Extending a similar concpet to a hypothetical full-field 25×33 mm2 mask area containgin 20 nm gate CDs shwos taht CD compensation, while computationally demanding, can be realized through a convolution approach of a 1×1 mm2 mask area using a non-uniform adaptive grid.

Paper Details

Date Published: 16 June 2003
PDF: 11 pages
Proc. SPIE 5037, Emerging Lithographic Technologies VII, (16 June 2003); doi: 10.1117/12.482344
Show Author Affiliations
Christof G. Krautschik, Association of Super-Advanced Electronics Technology (Japan)
Manish Chandhok, Intel Corp. (United States)
Guojing Zhang, Intel Corp. (United States)
Sang Hun Lee, Intel Corp. (United States)
Michael Goldstein, Intel Corp. (United States)
Eric M. Panning, Intel Corp. (United States)
Bryan J. Rice, Intel Corp. (United States)
Robert L. Bristol, Intel Corp. (United States)
Vivek Singh, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 5037:
Emerging Lithographic Technologies VII
Roxann L. Engelstad, Editor(s)

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