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Proceedings Paper

High-speed Viterbi decoding design for wireless LAN systems
Author(s): Xiaodan Gan; Zhongjun Wang; HongBao Zhang
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Paper Abstract

This paper describes the hardware design of a high speed Viterbi decoder for the IEEE 802.11a Wireless Local Area Networks (WLAN) application. A fully parallel Add-Compare-Select (ACS) and trace-back architecture is presented to achieve the decoding rate up to 54Mbps. Modulation scheme and coding rate dependent quntaization accuracy for soft decision Viterbi decoding is explored and a hardware implementation scheme with run-time configurable bit-length for soft decision is then proposed to reduce the system power consumption.

Paper Details

Date Published: 22 August 2002
PDF: 6 pages
Proc. SPIE 4911, Wireless and Mobile Communications II, (22 August 2002); doi: 10.1117/12.480523
Show Author Affiliations
Xiaodan Gan, Institute of Microelectronics (Singapore)
Zhongjun Wang, Institute of Microelectronics (China)
HongBao Zhang, Institute of Microelectronics (Singapore)


Published in SPIE Proceedings Vol. 4911:
Wireless and Mobile Communications II
Hequan Wu; Chih-Lin I; Jari Vaario, Editor(s)

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