Share Email Print
cover

Proceedings Paper

A vector DSP for digital media processing
Author(s): Bret Bersack; John Redford; Matt Moniz; Michael Goldman
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

A new chip using a DSP with a novel vector architecture is described. It uses a Very Dense Instruction Word (rather than a VLIW) and exploits the parallelism and narrow data typical of image processing to gain high performance at low cost and power. It contains eight 32-bit datapaths all working off a single instruction, and can do sixteen 16-bit MACs per cycle or four 32-bit memory accesses per cycle to 128 KB of on-chip memory. It also contains a serial datapath for handling low-performance code and OS functions. The chip includes memory, video and IO interfaces on an industry-standard bus. It also includes camera-specific IO such as videos DACs for NTSC/PAL and analog LCDs, an I2S audio interface, and USB 1.1. It is built in 0.18 um CMOS, runs at 233 MHz, and draws 300 mW. It uses no fixed-function blocks, microcode, or coprocessors, but can capture and compress video at 30 fps at VGA resolution using JPEG, or at CIF resolution using MPEG-4.

Paper Details

Date Published: 7 May 2003
PDF: 6 pages
Proc. SPIE 5022, Image and Video Communications and Processing 2003, (7 May 2003); doi: 10.1117/12.479727
Show Author Affiliations
Bret Bersack, ChipWrights, Inc. (United States)
John Redford, ChipWrights, Inc. (United States)
Matt Moniz, ChipWrights, Inc. (United States)
Michael Goldman, ChipWrights, Inc. (United States)


Published in SPIE Proceedings Vol. 5022:
Image and Video Communications and Processing 2003
Bhaskaran Vasudev; T. Russell Hsing; Andrew G. Tescher; Touradj Ebrahimi, Editor(s)

© SPIE. Terms of Use
Back to Top