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Proceedings Paper

Applications of CMOS processing to realize functional on-chip optical interconnects for VLSI
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Paper Abstract

VLSI/ULSI and the evolutions being driven by the International Technology Roadmap for Semiconductors (ITRS) are once again presenting severe challenges to the metal interconnect. Clock skew and other timing delays are becoming application critical design factors. The RC induced delays as well as parasitics (due to the trace density) are causing severe limitations to designs. Unfortunately these issues are very difficult to deal with using conventional computer aided design tools although efforts are being made, notably via DARPA funded programmes. We shall review techniques (and design elements) for on-chip optical communications. Through this we will present a new proposition for optical interconnects integrated upon otherwise conventional CMOS devices. We believe that the illustrated methodologies can be developed to provide very effective optical functionality appropriate to alleviating high-speed communications and timing issues.

Paper Details

Date Published: 30 May 2003
PDF: 4 pages
Proc. SPIE 4997, Photonics Packaging and Integration III, (30 May 2003); doi: 10.1117/12.479477
Show Author Affiliations
Terry V. Clapp, Univ. of Cambridge (United Kingdom)
Laurence W. Cahill, La Trobe Univ. (Australia)

Published in SPIE Proceedings Vol. 4997:
Photonics Packaging and Integration III
Randy A. Heyler; David J. Robbins; Ghassan E. Jabbour, Editor(s)

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