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Proceedings Paper

Defect inspection and repair reticle (DIRRT) design for the 100-nm and sub-100-nm technology nodes
Author(s): Nishrin Kachwala; Klaus Eisner
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Paper Abstract

Since pattern transfer is done via photomasks, they are critical to any process development. As a rule of thumb photomask development must keep I 8 months ahead of the wafer development pace in order that chipmakers meet the ITRS technology roadmap. This roadmap has been difficult to follow for the mask industry. While Lithography toolmakers have been successful in implementing technology changes to enhance resolution and maintain process enhancements with Optical Proximity Corrections (OPC) and Phase Shift Masks (PSM). The mask equipment industry has been slow to implement a technology switch due to its size and technical risks involved (1). Inspection and Repair of defects, to a mask manufacturer, are critical steps to the disposition of advanced photo masks. Masks that have gone through many critical processing steps or have been damaged in a production facility can most of the time be brought "back into specification" by verification inspection and repair thus enhancing yields which help to reduce cost of ownership. Yields in manufacturing can be increased by increasing productivity and equipment capability. Thus test mask are an integral part of tool development, monitoring, evaluation and acceptance. The design of the mask must have features sizes and layouts that are relevant to the tool under test or development. In this work our goal was to create a design that can be used for development and evaluation of inspection and repair tools for the I OOnm and sub I OOnm technology nodes.

Paper Details

Date Published: 16 August 2002
PDF: 10 pages
Proc. SPIE 4764, 18th European Conference on Mask Technology for Integrated Circuits and Microcomponents, (16 August 2002); doi: 10.1117/12.479340
Show Author Affiliations
Nishrin Kachwala, International SEMATECH (USA) and Conexant Systems Inc. (United States)
Klaus Eisner, International SEMATECH (USA) and Infineon Technologies (United States)

Published in SPIE Proceedings Vol. 4764:
18th European Conference on Mask Technology for Integrated Circuits and Microcomponents
Uwe F. W. Behringer, Editor(s)

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