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Proceedings Paper

Real-time hardware architectures for the bi-orthogonal wavelet transform
Author(s): Greg Knowles
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Paper Abstract

In this note we give a new architecture for the bi-orthogonal wavelet transform. The basis of our approach is a new convolver circuit that generates low and high pass values simultaneously in the forward transform, and combines low and high pass values in the inverse transform to produce even and odd data values. This is possible because of the symmetry of the bi-orthogonal wavelet coefficients and because the bi-orthogonal wavelet transform preserves the number of input data samples. The results are optimal in the sense of the number of multipliers used. The architecture given here is more efficient than lifting, for example in the case of the Daubechies 9-7 wavelet, lifting requires 6 multiplications per transformed (H, G) pair, while this method uses only 5. Note that the designs given here are fully pipelined and so are suitable for high-speed or low-power implementation.

Paper Details

Date Published: 14 April 2003
PDF: 8 pages
Proc. SPIE 5012, Real-Time Imaging VII, (14 April 2003); doi: 10.1117/12.477481
Show Author Affiliations
Greg Knowles, Flinders Univ. of South Australia (Australia)

Published in SPIE Proceedings Vol. 5012:
Real-Time Imaging VII
Nasser Kehtarnavaz; Phillip A. Laplante, Editor(s)

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