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Proceedings Paper

Threshold logic parallel counters for 32-bit multipliers
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Paper Abstract

In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.

Paper Details

Date Published: 14 November 2002
PDF: 10 pages
Proc. SPIE 4935, Smart Structures, Devices, and Systems, (14 November 2002); doi: 10.1117/12.477382
Show Author Affiliations
Peter Celinski, Univ. of Adelaide (Australia)
Sorin D. Cotofana, Delft Univ. of Technology (Netherlands)
Derek Abbott, Univ. of Adelaide (Australia)


Published in SPIE Proceedings Vol. 4935:
Smart Structures, Devices, and Systems
Erol C. Harvey; Derek Abbott; Vijay K. Varadan, Editor(s)

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