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Proceedings Paper

RET-compliant cell generation for sub-130-nm processes
Author(s): Juan Andres Torres; David Chow; Paul de Dood; Daniel J. Albers
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Paper Abstract

The use of Resolution Enhancement Technologies (RET) is becoming mainstream for sub-wavelength lithography processes. Optical tools will not likely meet the process requirements for sub-130nm designs on their own. Different RET are being explored and in some cases, heavily used in order to improve the process window of sub-wavelength imaging. Model-based OPC, sub-resolution assist feature and phase shift masks are some of the most common RET Methods used to achieve production-worthy imaging. Every RET has its own limitations and advantages for every specific one. Some designs will not be able to be subjected to a specific RET because the layout is not friendly to it. Manual redesign of such layouts becomes intractable for very complex design with multiple cell attractive from the process integration point of view. By analysis standard cell libraries from an RET compliance attractive from the process integration point of view. By analysis standard cell libraries from an RET compliance perspective, it is possible to envision a methodology that can find the most RET-friendly design while maintaining the functional specification of every cell. This investigation focuses on sub-resolution assist features, alternating phase shift masks and double dipole. For most common RET approaches, minimum spacing, placement, width and feature geometry can be extracted from the RET compliance analysis. Later, a set of enhanced design rules that incorporate RET specific constraints is used to re-derive the optimal feature arrangement within the cells, until the cell meets the level of RET compliance defined by the user. Eventually, the process can be extended to ful layout compliance when all the interactions between individual cells is accounted for, and modified accordingly. The advantage of having RET compliant cell sis that during lace and route, the use can concentrate on optimizing global placement parameters instead of focusing on each individual cell. The final results will depend on the user requirements and acceptable parameters of ear, power, manufacturability, etc. This a general flow that is able to generate cells that meet electrical and manufacturing specifications and it is flexible enough to accommodate every existing RET.

Paper Details

Date Published: 12 July 2002
PDF: 11 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475688
Show Author Affiliations
Juan Andres Torres, Mentor Graphics Corp. (United States)
David Chow, Mentor Graphics Corp. (United States)
Paul de Dood, Prolific Inc. (United States)
Daniel J. Albers, Prolific Inc. (United States)

Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Kenneth W. Tobin; Alexander Starikov, Editor(s)

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