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Proceedings Paper

Highly manufacturable capacitor-less 1T-DRAM concept
Author(s): Pierre C. Fazan; Serguei Okhonin; Mikhail Nagoga; Jean-Michel Sallese
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Paper Abstract

We introduce a new cell architecture for Dynamic Random Access Memory (DRAM) and embedded DRAM applications. By exploiting the Floating Body characteristics of partially depleted silicon on insulator (SOI) transistors, a capacitor-less DRAM cell structure can store and amplify the stored signal by using only a single transistor. Such a DRAM cell has a footprint two times smaller than that of standard DRAM cells and can be integrated in any CMOS process.

Paper Details

Date Published: 12 July 2002
PDF: 14 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475684
Show Author Affiliations
Pierre C. Fazan, Swiss Federal Institute of Technology Lausanne and Innovative Silicon Solutions (Switzerland)
Serguei Okhonin, Swiss Federal Institute of Technology Lausanne (Switzerland)
Mikhail Nagoga, Swiss Federal Institute of Technology Lausanne (Switzerland)
Jean-Michel Sallese, Swiss Federal Institute of Technology Lausanne (Switzerland)


Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Kenneth W. Tobin; Alexander Starikov, Editor(s)

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