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Proceedings Paper

Monte-Carlo methods for chemical-mechanical planarization on multiple-layer and dual-material models
Author(s): Yu Chen; Andrew B. Kahng; Gabriel Robins; Alexander Zelikovsky
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Paper Abstract

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, we seek to make a layout uniform with respect to prescribed density criteria, by inserting area fill geometries in to the layout. We review previous research on single-layer fill for flat and hierarchical layout density control based on the Interlevel Dielectric CMP model. We also describe the recent combination of CMP physical modeling and linear programing for multiple-layer density control, as well as the Shallow Trench Isolation CMP model. Our work makes the following contributions for the Multiple-layer Interlevel Dielectric CMP model. First, we propose a new linear programming approach with a new objective for the multiple-layer fill problem. Second, we describe modified Monte-Carlo approaches for the multiple- layer fill problem. Comparisons with previous approaches show that the new linear programming method is more reasonable for manufacturability, and that the Monte-Carlo approach is efficient and yields more accurate results for large layouts. The CMP step in Shallow Trench Isolation (STI) is a dual-material polishing process, i.e., multiple materials are being polished simultaneously during the CMP process. Simple greedy methods were proposed for the non- linear problem with Min-Var and Min-Fill objectives, where the certain amount of dummy features are always added at a position with the smallest density. In this paper, we propose more efficient Monte-Carlo methods for the Min-Var objective, as well a improved Greedy and Monte-Carlo methods for the Min-Fill objective. Our experimental experience shows that they can get better solutions with respect to the objectives.

Paper Details

Date Published: 12 July 2002
PDF: 12 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475677
Show Author Affiliations
Yu Chen, Univ. of California/Los Angeles (United States)
Andrew B. Kahng, Univ. of California/San Diego (United States)
Gabriel Robins, Univ. of Virginia (United States)
Alexander Zelikovsky, Georgia State Univ. (United States)

Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Alexander Starikov; Kenneth W. Tobin, Editor(s)

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