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Proceedings Paper

Impact of subwavelength CD tolerance on device performance
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Paper Abstract

We describe a new procedure of design qualification to ensure manufacturability of deep sub-wavelength circuits. The procedure is based on optical simulation of the layout, integrated with device simulation of the layout, integrated with device simulation to meet predefined conditions set forth by the layout control lines called tolerance contours, a new concept proposed in this work, are first defined for active devices based on the geometry-dependent, target MOSFET parameters, such as ION and IOFF and for interconnecting lines, based on the resolution of the etch process, misalignment and overlap or enclosure of metal and contact layers. Drawn geometries, OPC features, or exposure conditions are then adjusted such that the simulated silicon images would fall within the tolerance contours. The concept is demonstrated on SRAM cell shrink from 120 to 100 nm technology nodes.

Paper Details

Date Published: 12 July 2002
PDF: 8 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475673
Show Author Affiliations
Artur P. Balasinski, Cypress Semiconductor Corp. (United States)
Linard Karklin, Numerical Technologies, Inc. (United States)
Valery Axelrad, Sequoia Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Alexander Starikov; Kenneth W. Tobin Jr., Editor(s)

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