Share Email Print
cover

Proceedings Paper

GDS-3 initiative: advanced design-through-chip infrastructure for subwavelength technology
Author(s): Robert C. Pack; Mitchell D. Heins; Ahmad R. Chatila; Victor V. Boksha; D. Cottrell; C. Neil Berglund; J. Hogan; F. James; T. Vucurevich; M. Bales; K. Shimasaki
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In this paper we review current design-to-silicon manufacturing challenges and complexities confronting the IC design and manufacturing worlds as the industry prepares for sub-100nm technology node IC production and discuss a simplifying infrastructure and various principles for reducing and managing these complexities. Rapidly increasing overall complexity spanning all elements of the design- through-silicon 'ecosystem' and entanglement of the intricacies of traditionally separable design and manufacturing process technical disciplines is increasingly evident in long-loop design-mask-FAB iterations portending a widening of the design-productivity gap and an impact on the cost-effectiveness and productivity of the IC industry. Using the concept of 'technology overshoot' we conclude that the IC industry must broaden its development efforts and diversify investments to include those of building a robust and inherently simplifying interface infrastructure between design and manufacturing and to enable the efficiencies required of a maturing industry. We also explore the concept of modularity and how other mature industries have employed it to optimize efficiencies and investments and conclude that while the design and manufacturing worlds have practiced a number of fundamental concepts of modularity - the overall desegregation of the industry as a whole as case in point - a consistent, well-planed architecture for managing the interface between the two worlds has not yet been employed; hindering the development and migration of much needed productivity and cost-effectiveness enhancements. We then discus the impact of these factors on the industry in light of sub-wavelength era lithography resolution enhancement technologies and related manufacturing process and device physics issue, which increasingly impact the design flow. Recognizing that significant improvement to the design-silicon manufacturing interface is required, lastly we discuss a solution in the form of a new industry initiative called GDS-3. In our findings we acknowledge that the IC industry has already developed a solution, called OpenAccess, to a similar problem in the design space having to do with interoperability between design automation tools. We relate this work to the issues being faced between design and manufacturability and draw our final conclusion that the new design-to-manufacturing infrastructure should be an augmentation of the design community's Open Access initiative.

Paper Details

Date Published: 12 July 2002
PDF: 19 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475667
Show Author Affiliations
Robert C. Pack, Cadence Design Systems, Inc. (United States)
Mitchell D. Heins, Cadence Design Systems, Inc. (United States)
Ahmad R. Chatila, Cypress Semiconductor Corp. (United States)
Victor V. Boksha, Boksha Global Partners (United States)
D. Cottrell, Silicon Integration Initiative, Inc. (United States)
C. Neil Berglund, Northwest Technology Group (United States)
J. Hogan, Cadence Design Systems, Inc. (United States)
F. James, Cadence Design Systems, Inc. (United States)
T. Vucurevich, Cadence Design Systems, Inc. (United States)
M. Bales, Cadence Design Systems, Inc. (United States)
K. Shimasaki, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Kenneth W. Tobin; Alexander Starikov, Editor(s)

© SPIE. Terms of Use
Back to Top