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Proceedings Paper

Enabling the 70-nm technology node with 193-nm altPSM lithography
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Paper Abstract

The likely possibility of having to support the 70 nm technology node with 193 nm lithography is lithography. The extremely significant resolution challenges and the ability of strong resolution enhancement techniques (RET) to meet them, is discussed. Evidence is presented that all strong RET impact the design flow by imposing nontrivial design restrictions. Data from an in-depth alternating phase shifted mask design feasibility assessment, conducted on the poly-gate level of the 180 nm technology node, is presented to give an outlook on the feasibility of RET-enabled design flows. Anticipated complications in taking such RET-enabled design flows to the complexity required for multiple critical levels of the 70nm node are discussed. An EDA solution focusing on complete integration of RET layout manipulations into the design flow is contrasted to an approach focusing on complex, optimized design rule comprises.

Paper Details

Date Published: 12 July 2002
PDF: 12 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475663
Show Author Affiliations
Lars W. Liebmann, IBM Microelectronics (United States)
Jennifer Lund, IBM Microelectronics (United States)
Ioana C. Graur, IBM Microelectronics (United States)
Fook-Luen Heng, IBM Microelectronics (United States)
Carlos A. Fonseca, IBM Microelectronics (United States)
James Culp, IBM Microelectronics (United States)
Allen H. Gabor, IBM Microelectronics (United States)


Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Kenneth W. Tobin; Alexander Starikov, Editor(s)

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