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Proceedings Paper

Approaching the one billion transistor logic product: process and design challenges
Author(s): George E. Sery
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Paper Abstract

Microprocessor product density and performance trends have continued to follow the course predicted by Moore's Law. To support the trends in the future and build logic products approaching one billion or more transistors before the end of the decade, several challenges must be met. These challenges include: (1) maintaining transistor/interconnect feature scaling, (2) the increasing power density dilemma, (3) increasing relative difficulty of 2D feature resolution and general critical dimension control, (4) identifying cost effective solutions to increasing process and design database complexity. The trend in transistor scaling can be maintained while addressing the power density issue with new transistor structures exemplified by the Depleted Substrate Transistor incorporating a raised source-drain and high-K gate dielectric. The general 2D patterning and resolution control problems will require several solution approaches both through design and technology e.g. reduce design degrees of freedom, use of simpler arrayed structures, improved uniformity, improved tools, etc. The data base complexity/cost problem will require solutions likely to involve use of improved data structure, improved use of hierarchy, and improved software and hardware solutions.

Paper Details

Date Published: 12 July 2002
PDF: 8 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475662
Show Author Affiliations
George E. Sery, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Kenneth W. Tobin; Alexander Starikov, Editor(s)

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